IBIS Macromodel Task Group

Meeting date: 20 Mar 2007

Members (asterisk for those attending):
* Ambrish Varma, Cadence Design Systems
  Arpad Muranyi, Intel Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Doug White, Cisco Systems
  Ganesh Narayanaswamy, ST Micro
* Hemant Shah, Cadence Design Systems
* Ian Dodd, Mentor Graphics
* Joe Abler, IBM
* John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar, Cadence Design Systems
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
* Mike Steinberger, SiSoft
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
* Richard Ward, Texas Instruments
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence
  Stephen Scearce, Cisco Systems
  Syed Huq, Cisco Systems
* Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
* Vuk Borich, Agilent
* Walter Katz, SiSoft

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Call for patent disclosure:

No one declared a patent.

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Opens:

Michael Mirmak called from an airport and had potential time restrictions.

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Review of ARs:

- Mike document VHDL macro library and post to web site
  Some progress, but not yet done.

- Arpad: Write parameter passing syntax proposal for a possible BIRD
  TBD - On hold, Arpad returns in 4 weeks

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New Discussion:

Update on EDA vendor status:
- There are 2 or 3 issues to be resolved.
- Consulting with IP vendors on IP protection, etc.
- Another vendor meeting is scheduled for later this week.
  - Will have proposal after that.
- Agilent has joined, wants to be kept in the loop.
  - No document is in place to help newcomers catch up, working on that.

AR: Todd and Hemant advise the group about schedule for next meeting

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Next meeting: 27 Mar 2007 12:00pm PT